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fully associative cache cache coherency primary cache cache conflict cache Pipeline Burst Cache direct mapped cache i860 secondary cache SPARCstation 10 Translation Look-aside Buffer set associative cache meta-data backside cache cache line write-back Scalable Coherent Interface replacement algorithm virtual cache Smartdrive Intel i960 flush buffered write-through thrash Triton cache miss cache hit strided proxy server content addressable memory least recently used locality data mining data dictionary checksum Data Address Generator sector mapping data mart level two cache second level cache cache consistency cache block PB Cache level 1 cache level 2 cache level one cache Cy486SLC data main memory data structure Pipelined Burst Cache data bus data abstraction cache memory L1 cache L2 cache data flow data driven gate data model more...